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Stanford and MIT researchers emanate 3D CO nanotube CPU architecture

Researchers have grown a new CPU pattern that, they claim, could solve some of bandwidth issues severe chip design, and presumably even assistance extend Moore’s Law on silicon a small further.

The antecedent was built by a group of researchers from Stanford and MIT, that managed to mix memory, microprocessor and sensors onto a singular dissimilar section done of graphene nanotubes, with resistive RAM (RRAM) squished over a top. 

The 3D mechanism pattern is, a group claims, “the many formidable nano-electronic complement ever done with rising nano-technologies”.

Carbon has a aloft toleration to feverishness than silicon, and so regulating a CO nanotubes means that a chip can mount adult to aloft temperatures than a unchanging chip – generally now a wafers are removing so ridiculously thin.

The investigate saved by a Defense Advanced Research Projects Agency (DARPA) and a US National Sanitation Foundation (!) is creation good headway, though it is, for wish of a improved phrase, ‘not retrograde compatible’ and so it could be a while before we see anything in a shops that uses a same technology.

“The inclination are better: Logic done from CO nanotubes can be an sequence of bulk some-more energy-efficient compared to today’s proof done from silicon, and similarly, RRAM can be denser, faster, and some-more energy-efficient compared to DRAM,” pronounced Philip Wong from a MIT team.

The work has come on during a unusual pace, with a University of Winsconsin-Madison group initial perfecting a nanotube complement to pass speeds probable in silicon chips as recently as final September.

At that time, experts guess a chips could take a stream adult to 1.9 times that of a required silicon dewberry. Ultimately it’s suspicion that figure will boost to 5 times a speed, with a fifth of a energy, though again, no time frames.

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