Electronics industry consortium PCI-SIG has unveiled the specifications for PCle 4.0, the latest iteration of the high-speed serial computer expansion bus standard, which ought to be able to handle data from multiple GPUs.
The organisation said its latest specifications are capable of providing PCs and servers with data transfer rates of up to 16GTps [giga-transfers per second], and it’s already started work on version 5.0.
A 750 member-run organisation aimed at streamlining PC protocols, PCI-SIG normally releases major updates every four years.
And, despite the fact that development of 4.0 took some time, PCI-SIG chairman and president AI Yanes said that version 5.0 will launch in 2019, with both Intel and AMD rushing to support the new standard by then.
Highlights of PCle 4.0 include reduced system latency, lane margining, better reliability, availability, and serviceability (RAS) capabilities, lane margining, improved platform integration and extended tags for services devices.
Many companies will use the standard in areas such as storage network, and the fourth iteration could help reduce the price of high-speed NVMe SSDs. It could also bode well for 10GbE [gigabit ethernet] connections in a single lane.
There has been a lot of talk about PCle 4.0’s successor, with reports that the organisation has been fast-tracking development of 5.0 in recent months.
However, products based on the 5.0 standard may not actually appear until the early 2020s, and that’ll depend on how well companies conform to the standards.
Mainstream availability of products based on 4.0 will also be pretty thin until 2020. AMD is thought to be planning to use the technology in 2018, and the upcoming Intel Optane SSD 900p will likely come with 4.0 connectivity.
These, though, won’t appear for some time.
PCI-SIG president Al Yanes said: “I’m pleased to share that PCI-SIG has released the PCIe 4.0 Specification Version 1.0 and it is now available for download on our website.
“We had previously announced in June this year at our annual DevCon event that the Version 0.9 specification was feature complete and undergoing member IP review.
“The final published spec describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant.
“The delivery of the PCIe 4.0 specification to the industry is an important addition to our spec library as it delivers high performance 16GT/s data rates with flexible lane width configurations, while continuing to meet the industry’s requirements for low power.”
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