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​IEDM 2017: Intel inches closer to EUV lithography

There are many reasons why it is getting harder to produce leading-edge processors, but no roadblock is bigger than photolithography, the process of using light to transfer patterns to the wafer. The current tools are no longer capable of printing the smallest features–at least not without some time-consuming and costly extra steps–and the replacement, known as extreme ultra-violet or EUV lithography, is years behind schedule.

Lately there have been signs of progress and the industry is racing to bring EUV lithography into volume production. Samsung wants to be first, and next year at ISSCC it will announce results for an SRAM test chip manufactured on its 7nm process using EUV. GlobalFoundries will start 7nm production sometime in 2019 without EUV, but plans to quickly follow-up with new versions that use the technology. Foundry giant TSMC is holding out until 5nm.

Intel has also been testing EUV tools, reportedly at its D1X research fab in Hillsboro, Oregon, but the company still won’t say when it will use it for volume production. At IEDM 2017 last week, Intel gave a rare update on its progress with EUV and provided a few hints about how it will be deployed.

“EUV enables continued scaling,” said Intel’s Britt Turkot, a senior principal engineer in the lithography division. “It is highly desirable but will only be put in use when the technology is ready and cost effective.”

The size of the features that can be patterned with lithography is determined by two factors: the wavelength of the light and the numerical aperture of the system. The current tools use deep ultra-violet or DUV light with a wavelength of 193nm (as well as immersion to increase the numerical aperture since water has a higher refractive index than air). EUV, by contrast, uses light with a wavelength of 13.5nm enabling it to pattern much smaller features even with a lower numerical aperture.

At that wavelength, the photons of light are absorbed by just about any material so it needs to operate in a vacuum using a complex system of mirrors. “EUV is very complicated because everything changes in EUV,” Turkot said.

Until recently, the exposure source has been the primary problem because it needs to provide adequate power. A decade ago, the industry expected to reach the 250 watts required for volume production by the first half of 2013. But it wasn’t until this past summer at Semicon West that the manufacturer, the Dutch company ASML, announced it had demonstrated 250 watts thanks to recent advances in the Laser Produced Plasma (LPP) technology. That level has still not been matched in the field, though Turkot said she is confident that an upcoming tool upgrade will deliver 250 watts.

The exposure source, however, continues to cause issues with overall system uptime. The industry goal is 84 percent this year and 88 percent in 2018, but “we are lucky to be at 75 percent tool availability,” Turkot said, due to long periods of unscheduled downtime.

The ecosystem of tools and materials around EUV lithography is falling into place. Of the eight key projects in EUV infrastructure, six are largely completed. Suppliers are now producing blanks (the base material for photomasks) with single-digit defects and Intel’s own mask shop is running an EUV mask pilot line that has been able to produce 10nm and 7nm masks with no printable defects.

But masks that start out defect-free can end up with defects due to fall-on particles in the scanner leading to yield problems, which is why a protective pellicle–an infrastructure project still in development–is some important. Eventually the industry will need a tool that can see these tiny defects, known as Actinic Patterned Mask Inspection, but this final project “still has significant gaps.”

One area where there is little question of EUV’s value is resolution. Intel’s EUV pilot line has already achieved good patterning results for critical dimensions with accurate alignment. But Turkot said that edge placement error has become the biggest challenge to scaling features below 10nm. “You need to make sure that the features that should touch do and the those that should not touch do not,” she explained. EUV has great potential to address this problem because of its high resolution for greater pattern fidelity and because it minimizes multi-patterning steps, though other sources of edge placement error in the fab will need to be dealt with too.

Despite the progress, Intel still isn’t ready to say exactly when it will introduce EUV lithography in volume production. When it does, though, it be in a mix-and-match arrangement with the current 193nm immersion tools. Turkot said that because EUV is so expensive, Intel will use it only where it can replace three or more multi-patterning steps with a single exposure. We now know that at 10nm Intel has resorted to quadruple patterning for a few layers, so EUV can’t come soon enough.

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